Conventional tests for multi-bit memory devices have been modified by connecting several data input pins. Accordingly, the time required to test the memory device can be reduced because multiple data inputs can be tested simultaneously. In particular, these memory devices include a circuit allowing data from a single data input buffer to be provided to a plurality of data input bus lines during a memory test operation. The number of input-output pins needed to test the memory device can thus be reduced because one input-output pin can be used to provide data input to multiple data input bus lines. Because the input bus lines connected to the common input pin will have the same data input, a common data pattern is used during the test.
FIG. 1 is a circuit diagram of a merge data input circuit according to the prior art. As shown, this circuit includes data input buffers 3, 5, 7, and 9; data input bus lines 100, 200, 300, and 400; transfer gates 21, 23, 25, 27, 29, and 31; and merge data output signal generator 11. Each of the data input bus lines is connected to a respective data input buffer to which data inputs DI0, DI1, DI2, and DI3 are provided. The transfer gates 21, 23, and 25 control the connection between input bus lines 200, 300, and 400 and the data input buffers 5, 7, and 9. The transfer gates 27, 29, and 31 control the connections between the data input bus line 100 and the data input bus lines 200, 300, and 400. The merge data output signal generator 11 is connected to the transfer gates thus controlling the data provided to the data input bus lines 200, 300, and 400.
FIG. 2 is a circuit diagram illustrating a merge data output circuit according to the prior art. As shown, this circuit includes data output bus lines 500, 600, 700, and 800; an exclusive NOR gate 33; NAND gate 35; and switching units 37 and 39. Each of the data output bus lines connects a respective data signal DO0, DO1, DO2, and DO3 with a respective data output buffer 51, 53, 55, and 57. Each input of the exclusive NOR gate 33 is connected to a respective data output bus line so that the NOR gate performs an exclusive NOR operation with the data DO0, DO1, DO2, and DO3. The merge data output signal MDQ and the output of the exclusive NOR gate are provided to the inputs of the NAND gate 35. The switching unit 37 is provided to connect the data output bus line 500 with the data output buffer under the control of the merge data output signal MDQ. The switching unit 39 is connected in parallel with the switching unit 37 to connect the data output bus line 500 with the data output buffer 51 in response to the output of the NAND gate 35.
The circuits of FIGS. 1 and 2 may reduce the time required to test a memory device because multiple input and output data bus lines can be tested simultaneously using a single input pin and a single output pin. Faults caused by shorts between the data input bus lines or between the data output bus lines may go undetected, however, because each of these data lines is tested using a common data value. Accordingly, faults caused by shorts between data bus lines may go undetected until a test of the packaged memory device can be performed after fabrication, thereby increasing the costs of testing. Furthermore, the memory test circuits discussed above may be unable to provide a fail point screen according to a data pattern.